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History Of Your Computer

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Now we introduce a 'high speed' memory with a cycle time of, say 250 nanoseconds between the CPU and the core memory. When we request the first instruction, at location 100, the cache memory requests addresses 100,101,102 and 103 from the core memory all at the same time, and retains them 'in cache'. Instruction 100 is passed to the CPU for processing, and the next request, for 101, is filled from the cache. Similarly 102 and 103 are handled at the much increased repeat speed of 100 ns. In the meantime the cache memory has requested the next 4 addresses, 104 to 107. This continues until the predicted 'next location' is incorrect. The process is then repeated to reload the cache with data for the new address range. A correctly predicted address, when the requested location is in cache is known as a cache 'hit'.

If the main memory is not core, but a slower chip memory, the gains are not as great, but still an improvement. Expensive high speed memory is only required for a fraction of the capacity of the cheaper main memory. Also programmers can design programs to suit the cache operation, for instance by making a branch instruction in a loop take the next instruction for all cases except the final test, maybe count=0, when the branch occurs.

Now consider the speed gains to be made with disks. Being a mechanical device, a disk works in milliseconds, so loading a program or data from disk is extremely slow in comparison, even to core memory - 1000 times faster! Also there is a seek time and latency to be considered. (This is covered in another article on disks.)

You may have heard the term DMA in relation to PCs. This refers to Direct Memory Access. Which means that data can be transferred to or from the disk directly to memory, without passing through any other component. In a mainframe computer, typically the I/O or Input/Output processor has direct access to memory, using data placed there by the Processor. This path is also boosted by using cache memory.

In the PC, the CPU chip now has built-in cache. Level 1, or L1, cache is the primary cache in the CPU which is SRAM or Static RAM. This is high speed (and more expensive) memory compared to DRAM or Dynamic RAM, which is used for system memory. L2 cache, also SRAM, may be incorporated in the CPU or externally on the Motherboard. It has a larger capacity than L1 cache.

History Of Your Computer

To write a 1 in address 0 we would need to write a 1 bit in bit 0 of address 0000 0000 0000. All other bits would be zero. We would need to enable address lines X-0 and Y-0 by passing a small pulse through them, each pulse being half the size needed to flip the magnetic field. The one point where the two address lines pass through the same core would therefore cause a flip, as the sum of the two address line pulses is sufficient for this to happen.

On each plane we have a 'write inhibit' wire passing through all cores in that plane. To write a 1 bit we do not use this wire, however to write a zero in the other bit planes we pass an 'inhibit write' pulse. This pulse reduces the effect of the two address lines, such that there is insufficient current to flip the magnetic field, and the value remains at zero.

No other core will flip as we need all three components, two address lines, plus no 'inhibit write', pulse to flip the magnetic field, if required. The addressed core is the only one to have both address wires active, and so is the only one which will flip for a one bit, or remain at 0 if the 'inhibit write' pulse is present.

Now, how do we read this data? As mentioned above we have a sense wire, which passes through all cores in each plane. We use the address lines as before to select one core in each plane. If the core is set to a 1, it will flip to 0, the change in magnetic field will induce a pulse in the sense wire, which will be read as a 1 bit. This action is similar to a generator, where a changing magnetic field induces a current in the coil. If the value is zero, it will remain so.

This type of read is called a 'destructive readout', because the location which was read is now all zeros. For this reaon, the data is written back to the location in the next memory cycle. A subsequent write of data will also require a prior read, to set the state to all zeros.

Core memory has one big advantage over the 'chip memory' currently in use, in that it is non-volatile. This means it retains its data even if power is removed. A computer may be restarted after being powered off, with all data intact. You may be familiar with the term NVRAM, typically used in the BIOS or preset data in your home PC. NVRAM stands for Non Volatile Random Access Memory, In this case it is a bit of a cheat, as it needs a battery to maintain the data when power is removed. (BIOS means Basic Input Output System, the subject of a later article).

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