We start with the instruction in location 000. The processor requests this instruction by setting the address register to 000 and sending a request to memory. The first instruction is loaded into the P register. The first 3 bits tell the logic this is a STORE instruction, and enable gates to take the value in the next 3 bits, and place it in the register decoded from the last 3 bits. We place 3 in register 0. Instruction complete, get next instruction (add 1 to address register).
The next instruction, from 001, is also a STORE, and we load a value of 4 into register 1.
The third instruction, from 010, is an ADD. We add the contents of register 000 (3) to register 010 (initially 0) giving 3 in register 010.
Next, from 011, we have a SUBTRACT, which is used to count down. This would normally not require a separate instruction, but we use it here to demonstrate the principle. We subtract a value of 1 from register 001 going from 4 to 3.
The next instruction, from 100, the BRANCH, checks the count, in register 001 (second 3 bits) looking for not equal to zero. The data in register 3 is not zero, so we enable the last 3 bits, 010 to the ADDRESS register. Now the next instruction will come from location 010, not the next sequential address. This is the Branch out of sequence.
With an address of 010, the next instruction is the ADD again, which adds another 3 to register 010 totaling 6. We again subtract 1 from the count, check for not zero, and return once more to address 010. when we have added 3 on the fourth time through the loop, the count goes to zero, the BRANCH test fails, so, instead of branching, we take the next instruction in sequence, and STOP.
With any luck the RESULT in register 010 will be 12, which is the area of a 3x4 rectangle. We can calculate any area by substituting the dimensions in the STORE instructions.
The area around the instruction decode area is where the ingenuity of the logic designer shows. With a fixed number of bits in the instruction to play with, though of course more than the 9 bits we have used here, he must make the most of what there is. Working against this is the cost of incorporating complicated logic in the overall layout of the system, and the possible problems which may arise with unforeseen applications, or sequences of instructions.
Also to be considered is the instruction stack, or pipeline. As we saw in the article on cache memory, a speed increase can be obtained by fetching 4 instructions at once. We can go one step further and load these instructions into the processor. It is then possible to start working on the next instructions before the current one is finished. However if the current instruction performs a branch, this work must be discarded.
